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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6726D/D
128K x 8 Bit Fast Static Random Access Memory
The MCM6726D is a 1,048,576 bit static random access memory organized as 131,072 words of 8 bits. Static design eliminates the need for external clocks or timing strobes. Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems. This device meets JEDEC standards for functionality and revolutionary pinout, and is available in a 400 mil plastic small-outline J-leaded package. * * * * * * Single 5 V 10% Power Supply Fully Static -- No Clock or Timing Strobes Necessary All Inputs and Outputs Are TTL Compatible Three State Outputs Fast Access Times: 8, 10, 12 ns Center Power and I/O Pins for Reduced Noise
MCM6726D
WJ PACKAGE 400 MIL SOJ CASE 857A-02
PIN ASSIGNMENT
A A A A E DQ DQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A A A A G DQ DQ VSS VCC DQ DQ A A A A A
BLOCK DIAGRAM
A A A A A A A A A DQ INPUT DATA CONTROL DQ A A COLUMN I/O COLUMN DECODER ROW DECODER MEMORY MATRIX 512 ROWS x 256 x 8 COLUMNS VCC VSS
VCC VSS DQ DQ W A A A A
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . Address Input E . . . . . . . . . . . . . . . . . . . . . . Chip Enable W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable DQ . . . . . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
A
A
A
A
A
A
E W G
10/9/96
(c) Motorola, Inc. 1996 MOTOROLA FAST SRAM
MCM6726D 1
TRUTH TABLE (X = Don't Care)
E H L L L G X H L X W X H H L Mode Not Selected Output Disabled Read Write VCC Current ISB1, ISB2 ICCA ICCA ICCA Output High-Z High-Z Dout High-Z Cycle -- -- Read Cycle Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature -- Plastic Symbol VCC Vin, Vout Iout PD Tbias TA Tstg Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 1.2 - 10 to + 85 0 to + 70 - 55 to + 125 Unit V V mA W C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 - 0.5* Typ 5.0 -- -- Max 5.5 VCC + 0.3** 0.8 Unit V V V
* VIL (min) = -0.5 V dc; VIL (min) = -2.0 V ac (pulse width 2.0 ns) for I 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width 2.0 ns) for I 20.0 mA.
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH, Vout = 0 to VCC) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 Max 1.0 1.0 0.4 -- Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Active Supply Current (Iout = 0 mA) (VCC = max, f = fmax) Active Quiescent Current (E = VIL, VCC = max, f = 0 MHz) AC Standby Current (E = VIH, VCC = max, f = fmax) CMOS Standby Current (VCC = max, f = 0 MHz, E VCC - 0.2 V, Vin VSS + 0.2 V, or VCC - 0.2 V) Symbol ICCA ICC2 ISB1 ISB2 6726D-8 195 100 60 20 6726D-10 175 100 60 20 6726D-12 165 100 60 20 Unit mA mA mA mA 1, 2, 3 Notes 1, 2, 3
NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V). 2. All addresses transition simultaneously low (LSB) and then high (MSB). 3. Data states are all zero.
MCM6726D 2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Address Input Capacitance Control Pin Input Capacitance Input/Output Capacitance Symbol Cin Cin CI/O Typ -- -- -- Max 6 6 8 Unit pF pF pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to +70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a
READ CYCLE TIMING (See Notes 1 and 2)
6726D-8 Parameter Read Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Output Enable Low to Output Active Enable High to Output High-Z Symbol tAVAV tAVQV tELQV tGLQV tAXQX tELQX tGLQX tEHQZ Min 8 -- -- -- 3 3 0 -- Max -- 8 8 4 -- -- -- 4 6726D-10 Min 10 -- -- -- 3 3 0 -- Max -- 10 10 5 -- -- -- 5 6726D-12 Min 12 -- -- -- 3 3 0 -- Max -- 12 12 6 -- -- -- 6 Unit ns ns ns ns ns ns ns ns 4,5,6 4,5,6 4,5,6 Notes 3
Output Enable High to Output High-Z tGHQZ -- 4 -- 5 -- 6 ns 4,5,6 NOTES: 1. W is high for read cycle. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All read cycle timings are referenced from the last valid address to the first transitioning address. 4. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from device to device. 5. Transition is measured 200 mV from steady-state voltage with load of Figure 1b. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL). 8. Addresses valid prior to or coincident with E going low.
TIMING LIMITS
+5 V OUTPUT Z0 = 50 RL = 50 VL = 1.5 V OUTPUT 255 5 pF 480 The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
(a) Figure 1. AC TEST LOADS
(b)
MOTOROLA FAST SRAM
MCM6726D 3
READ CYCLE 1 (See Note 7)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Note 8)
tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQV tGLQX Q (DATA OUT) DATA VALID tGHQZ tEHQZ
MCM6726D 4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
6726D-8 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Address Valid to End of Write, G High Write Pulse Width Write Pulse Width, G High Data Valid to End of Write Data Hold Time Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tAVWH tWLWH, tWLEH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 8 0 8 7 8 7 4 0 -- 3 0 Max -- -- -- -- -- -- -- -- 4 -- -- 6726D-10 Min 10 0 9 8 9 8 5 0 -- 3 0 Max -- -- -- -- -- -- -- -- 5 -- -- 6726D-12 Min 12 0 10 9 10 9 6 0 -- 3 0 Max -- -- -- -- -- -- -- -- 6 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns 4,5,6 4,5,6 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady-state voltage with load of Figure 1b. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tWHQX tDVWH DATA VALID tWHDX tWHAX
MOTOROLA FAST SRAM
MCM6726D 5
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
6726D-8 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Enable to End of Write Data Valid to End of Write Data Hold Time Write Recovery Time Symbol tAVAV tAVEL tAVEH tELEH, tELWH tDVEH tEHDX tEHAX Min 8 0 7 7 4 0 0 Max -- -- -- -- -- -- -- 6726D-10 Min 10 0 8 8 5 0 0 Max -- -- -- -- -- -- -- 6726D-12 Min 12 0 9 9 6 0 0 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 4,5 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX tELWH tEHAX
Q (DATA OUT)
HIGH-Z
ORDERING INFORMATION
(Order by Full Part Number) MCM 6726D WJ
Motorola Memory Prefix Part Number
XX
X
Shipping Method (R = Tape and Reel, Blank = Rails) Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns) Package (WJ = 400 mil SOJ)
Full Part Numbers -- MCM6726DWJ8 MCM6726DWJ8R
MCM6726DWJ10 MCM6726DWJ10R
MCM6726DWJ12 MCM6726DWJ12R
MCM6726D 6
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
32-LEAD 400 MIL SOJ CASE 857A-02 F 32 PL 0.17 (0.007) N
32 17
S
TB
S
A
S
D 32 PL 0.17 (0.007) S DETAIL Z
TB
S
A
S
NOTE 3
1
16
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TO BE DETERMINED AT PLANE -T-. 4. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION A & B INCLUDE MOLD MISMATCH AND ARE DETERMINED AT THE PARTING LINE. DIM A B C D E F G K L N P R S INCHES MIN MAX 0.820 0.830 0.395 0.405 0.128 0.148 0.016 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.035 0.045 0.025 BSC 0.030 0.045 0.435 0.445 0.365 0.375 0.030 0.040 MILLIMETERS MIN MAX 20.83 21.08 10.03 10.29 3.75 3.26 0.50 0.41 2.48 2.24 0.81 0.67 1.27 BSC 1.14 0.89 0.64 BSC 1.14 0.76 11.05 11.30 9.52 9.27 1.01 0.77
-AL G
0.17 (0.007)
S
TA
S
B
S
P -BE
0.10 (0.004)
C
K
DETAIL Z
-T-
SEATING PLANE
R 0.25 (0.010)
S
S RADIUS TA
S
B
S
NOTE 3
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MOTOROLA FAST SRAM
MCM6726D/D MCM6726D 7

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